Are the first bits in a resistor ladder?

In the Pro iDSD/Pro iDSD Signature we are running 4 actual DACs in parallel with interleaving, meaning the net result is closer to 8 bit via multi-bit. That means the top 36dB (6bit) / 48dB (8 bit) are handled by a multi-bit architecture. As delta-sigma modulators struggle at high levels, we are removing the main disadvantage of DS, and we are avoiding the need for high order modulators.

Now multi-bit systems have the opposite problem of delta-sigma, meaning the are not very good at very low levels, and multi-bit struggles most at very low levels (around zero crossing). By splitting low level signals off into a low order delta-sigma modulator, you get the best of both worlds.

So the top 6-8 bit in iFi gear are processed as multi-bit, including the option to apply no digital filter. The lower bits are processed as delta-sigma over-sampled to what is in effect DSD256 (11.2/12.3MHz) again, it is possible to not apply any digital filtering.

This whole topic was covered here:

https://www.audiostream.com/content/qa-thorsten-loesch-amrifi

Around half way down the page, search for: “The DAC chip we use in the iDSD nano offers a rather unusual way to handle things.”

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